(1) Field of the Invention
This invention relates generally to digital filters and, more particularly, to second order recursive digital filters including circuitry for eliminating limit cycles.
(2) Description of the Prior Art
When a recursive digital filter is implemented using fixed point arithmetic, errors occur due to quantization of the products. With a constant input to a feedback section of the filter, these errors can lead to small periodic oscillations called limit cycles, at the output of the filter. The amplitude of these limit cycles (which are to be distinguished from the large limit cycles associated with an overflow condition) is a determining factor in the idle channel behavior of the filter, and accordingly affect the internal word length requirements and ultimately the cost of the filter.
Limit cycles have been discussed extensively by many authors. See, for example, "A Bound on Limit Cycles in Fixed-Point Implementations of Digital Filters", I. W. Sandberg and J. F. Kaiser, IEEE Trans. Audio and Electroacoustics, Vol. AU-20, No. 2, June, 1972; "An Absolute Bound on Limit Cycles Due to Roundoff Errors in Digital Filters", J. L. Long and T. N. Trick, IEEE Trans. Audio and Electroacoustics, Vol. AU-21, No. 1, Feb., 1973; and "Some Remarks on the Classification of Limit Cycles in Digital Filters", T. A. C. M. Classen et al, Phillips Research Reports, 28, pp 297-305, 1973. Still other pertinent references are cited in U.S. Pat. No. 3,906,199 issued to R. B. Kieburtz and K. V. Mina on Sept. 16, 1975.
While most authors have tried to estimate or bound the peak amplitude, rms value, or the fundamental frequency of limit cycles, the approach by Kieburtz et al disclosed in the aforesaid patent is significantly different. In that patent, limit cycle noise in a second order recursive digital filter is reduced by a circuit which randomly inhibits the rounding signal in one of the digital multipliers disposed in the filter. While the Kieburtz et al. technique has indeed been found advantageous in many instances, it has nevertheless been found that for certain signal values and filter constraints, even longer transients or limit cycles may result. Additionally, the patentees' filter design is not equipped to eliminate half sampling rate or dc limit cycles which exhibit special properties that make suppression more difficult.
Based upon the foregoing, it is the broad object of the present invention to improve the performance and reduce the cost of digital filters by eliminating limit cycle noise. Specific objects are the reduction of limit cycles including dc or half-sample rate limit cycles, for the case of zero input to the filter.